晶太 (Jīngtài, also known as J.Y. Company)'s proprietary ASIC is used for their later single-game cartridges as well as for most of their multicarts. Due to its latter purpose, it allows flexibly switching between several PRG and CHR banking modes, supports ROM nametables, and permits specifying the CIRAM bank for each nametable separately (Extended Mirroring), automatic MMC4-like CHR bankswitching, and a very flexible IRQ counter. It is part of several iNES/NES 2.0 mappers which differ in their PCB configuration:
Mask: $FFFF D~7654 3210 --------- JJ.. .... ++-------- Jumper/solder pad configuration
Depending on the game, the jumper setting selects different title screens or game counts on multicarts. Apparently, the address of this register is fully decoded, as the SC-128 version of Final Fight 3, which otherwise happily randomizes the masked-off address bits, keeps A0-A11 constantly at zero to read from this register.
Mask: $F803 $5800 write: Write operand 1 $5801 write: Write operand 2 and start multiplying $5800 read: Read result LSB $5801 read: Read result MSB
After writing the two operands to $5800 and $5801, the result can be read eight M2 cycles later; if the registers are read from earlier than that, intermediate results are obtained.
Mask: $F803 $5802 write: Increase accumulator by written value $5803 write: Reset accumulator to 0 and set test register to written value $5802 read: Read accumulator value $5803 read: Read test register
Mask: $F803. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing range $8000-87FF).
D~7654 3210 --------- .PPP PPPP +++-++++- Select PRG-ROM bank number
In 8 KiB PRG banking mode:
In 16 KiB PRG banking mode:
In 32 KiB PRG banking mode:
If $D000 bit 2 is clear, the 8/16/32 KiB bank at $E000/$C000/$8000-$FFFF is hard-wired to the last bank within the outer bank. Furthermore, if register $D000 bit 7 is set, $8003 also selects an 8 KiB PRG-ROM bank at CPU $6000-$7FFF, which is
The PRG-ROM bank selected via $8000-$8003 is always masked to the outer bank size (512/256/128 KiB, depending on PCB/mapper number). Accessing more than that requires manipulating the Outer Bank register at $D003.
Mask: $F807. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $9000-97FF and $A000-A7FF).
In 8 KiB CHR banking mode:
In 4 KiB CHR banking mode with MMC4 mode off:
In 4 KiB CHR banking mode with MMC4 mode on:
In 2 KiB CHR banking mode:
In 1 KiB CHR banking mode:
The CHR bank selected via $9000-$A007 is always masked to the outer bank size (512/256/128 KiB, depending on PCB/mapper number and $D003 value). Accessing more than that requires manipulating the Outer Bank register at $D003. If MMC4-like bankswitching mode is enabled via $D003 bit 7, the latch is set to 0 when the PPU reads from $0FD8-$0FDF/$1FD8-$1FDF and to 1 when the PPU reads from $0FE8-$0FEF/$1FE8-$1FEF.
Mask: $F807. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $B000-B7FF).
These registers have no function if neither ROM nametables ($D000 bit 5) nor Extended Mirroring ($D001 bit 3) are enabled, or their function is supressed via a jumper on some PCB variants that are denoted by iNES Mapper 090.
If Extended Mirroring is enabled ($D001 bit 3 set):
If ROM nametables are enabled ($D000 bit 5 set) for all nametables ($D000 bit 6 set):
If ROM nametables are enabled ($D000 bit 5 set) for selected nametables ($D000 bit 6 clear):
This means that enabling ROM nametables via $D005 bit 5 and all $B00x registers having bit 7 match $D002 bit 7 effectively duplicates the functionality of Extended Mirroring ($D001 bit 3).
Mask: $F007. Writes are accepted even if address bit 11 is set. $C000: IRQ Disable/Enable $C001: IRQ Mode/Flags $C002: IRQ Disable $C003: IRQ Enable $C004: Set prescaler value (*) $C005: Set counter value (*) $C006: Set XOR value $C007: Configure unknown mode (*) The written value is XORed with the content of register $C006 before being stored.
"Disabling" acknowledges a pending IRQ, inhibits counting, and resets the prescaler to zero. "Enabling" means that counting is no longer inhibited, and IRQs will be generated once prescaler and counter wrap.
D~7654 3210
---------
.... ...I
+- Disable (0)/Enable (1) IRQ generation.
D~7654 3210
---------
DD.. FPSS
|| ||++- Select IRQ source
|| || 0: CPU M2 rise
|| || 1: PPU A12 rise (unfiltered, eight per scanline)
|| || 2: PPU reads (170 per scanline)
|| || 3: CPU writes
|| |+--- Select prescaler mask
|| | 0: $FF
|| | 1: $07
|| +---- Disable (0)/Enable (1) $C007 mode.
++-------- Select counting direction
0: Counting disabled
1: Increase
2: Decrease
3: Counting disabled
Mask: $F007. Writes are accepted even if address bit 11 is set.
This register is used together with register $C001 bit 3. Its functionality is not known, and no known game uses it.
Mask: $F803. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $D000-D7FF).
D~7654 3210
---------
6GRC CLPP
|||| ||++- Select PRG-ROM banking mode
|||| || 0: 32 KiB banking
|||| || 1: 16 KiB banking
|||| || 2: 8 KiB banking
|||| || 3: 8 KiB banking, but with bank numbers bits 0-6 reversed
|||| |+--- Select bank $8000-(32 KiB)/$C000-(16 KiB)/$E000-(8KiB)-$FFFF
|||| | 0: Hard-wired to last bank
|||| | 1: Switchable via $8003
|||+-+---- Select CHR banking mode
||| 0: 8 KiB banking
||| 1: 4 KiB banking
||| 2: 2 KiB banking
||| 3: 1 KiB banking
||+------- Select ROM nametable status
|| 0: ROM nametables disabled
|| 1: ROM nametables enabled (for all or some nametables, depending on bit 6)
|+-------- Select ROM nametable selection method if R=1, ignored otherwise
| 0: ROM nametables selected separately by $B00x bit 7 XOR $D002 bit 7
| 1: ROM nametables enabled globally for all nametables
+--------- Select CPU $6000-$7FFF mapping
0: Map WRAM, if present, otherwise open bus
1: Map 8 KiB PRG-ROM bank selected via $8003
(appropriately shifted and right-filled with binary 1 in 16/32 KiB PRG modes)
Mask: $F803. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $D000-D7FF).
D~7654 3210
---------
.... E.MM
| ++- Select nametable mirroring type if E=0 and $D000 bit 5=0
| 0: Vertical
| 1: Horizontal
| 2: One-screen, page 0
| 3: One-screen, page 1
+---- Select Extended Mirroring
0: Disabled, use MM bits
1: Enabled, ignore MM bits, use $B000-$B003 bit 0
Mask: $F803. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $D000-D7FF).
D~7654 3210
---------
RW.. ....
|+-------- CHR write-enable
| 0: disabled, CHR memory is write-protected
| 1: enabled, CHR memory is write-enabled
+--------- Define ROM nametable selection. Functional only if ROM nametables are
generally enabled, but individually selected ($D000 bit 5 set and
$D000 bit 6 clear)
0: $B00x bit 7=0 selects CIRAM, $B00x bit 7=1 selects ROM nametable
1: $B00x bit 7=1 selects CIRAM, $B00x bit 7=0 selects ROM nametable
Note: x=0..3
Bit 6 only matters when using CHR-RAM.
Mask: $F803. This means that writes are ignored if address bit 11 is set (i.e. these registers extend only through addressing ranges $D000-D7FF).
The exact meaning of this register depends on the PCB, specified by the mapper number.
D~7654 3210 --------- 4.MM MMMM | ++-++++- PCB/Mapper-specific +--------- Select MMC4-like automatic CHR-ROM bankswitching mode 0: Disable 1: Enable (only meaningful in 4 KiB CHR-ROM banking mode)
Mask: $F803. This means that writes are ignored if address bit 11 is set.
D~7654 3210 --------- 4.Lc cPPC | || |||+- If L=0: Select 256 KiB outer CHR-ROM bank (CHR A18), ignored if L=1 | || |++-- Select 512 KiB outer PRG-ROM bank (PRG A19-A20) | |+-+---- Select 512 KiB outer CHR-ROM bank (CHR A19-A20) | +------- Select outer CHR-ROM bank size | 0: Mask $900x/$A00x to 256 KiB, use C | 1: Mask $900x/$A00x to 512 KiB, ignore C +--------- Select MMC4-like automatic CHR-ROM bankswitching mode 0: Disable 1: Enable (only meaningful in 4 KiB CHR-ROM banking mode)