| Company | Nintendo, others |
| Games | 390 in NesCartDB |
| Complexity | ASIC |
| Boards | SKROM, SLROM, SNROM, others |
| Pinout | MMC1 pinout |
| PRG ROM capacity | 256 KiB (512 KiB) |
| PRG ROM window | 16 KiB + 16 KiB fixed or 32 KiB |
| PRG RAM capacity | 32 KiB |
| PRG RAM window | 8 KiB |
| CHR capacity | 128 KiB |
| CHR window | 4 KiB + 4 KiB or 8 KiB |
| Nametable mirroring | H, V, or 1, switchable |
| Bus conflicts | No |
| IRQ | No |
| Audio | No |
| iNES mappers | 001, 105, 155 |
The Nintendo MMC1 is a mapper ASIC used in Nintendo's SxROM, NES-EVENT and 2ME circuit boards. It first appeared in the April of 1987.
iNES Mapper 1 and 155 denote the SxROM and 2ME circuit boards mounting the MMC1B (iNES Mapper 1) or MMC1A (iNES Mapper 155) revision of the ASIC; Mapper 1 is used if the revision is not known or irrelevant. Two submappers of mapper 1/155 are valid:
All other SxROM variants are denoted by their functional PRG/CHR-ROM/RAM sizes in the NES 2.0 header. Without NES 2.0, the PRG-RAM size has to be assumed; 32 KiB are sufficient for compatibility with all known titles.
INES Mapper 105 denotes the NES-EVENT circuit board.
Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG-ROM banks or to set up 32 KB PRG bankswitching (like BNROM), but most games use the default setup, which is similar to that of UxROM.
Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce its pin count. CPU $8000-$FFFF is connected to a common shift register. Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state. To change a register's value, the CPU writes five times with bit 7 clear and one bit of the desired value in bit 0 (starting with the low bit of the value). On the first four writes, the MMC1 shifts bit 0 into a shift register. On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register. Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper doesn't see the lower address bits (similar to the mirroring seen with PPU registers). After the fifth write, the shift register is cleared automatically, so writing again with bit 7 set to clear the shift register is not needed.
To switch a bank, a program will execute code similar to the following:
;
; Sets the switchable PRG-ROM bank to the value of A.
;
; A MMC1_SR MMC1_PB
setPRGBank: ; 000edcba 10000 Start with an empty shift register (SR). The 1 is used
sta $E000 ; 000edcba -> a1000 to detect when the SR has become full.
lsr a ; >0000edcb a1000
sta $E000 ; 0000edcb -> ba100
lsr a ; >00000edc ba100
sta $E000 ; 00000edc -> cba10
lsr a ; >000000ed cba10
sta $E000 ; 000000ed -> dcba1 Once a 1 is shifted into the last position, the SR is full.
lsr a ; >0000000e dcba1
sta $E000 ; 0000000e dcba1 -> edcba A write with the SR full copies D0 and the SR to a bank register
; 10000 ($E000-$FFFF means PRG bank number) and then clears the SR.
rts
But because only the fifth write sets the destination register, the following equivalent (if obfuscated) subroutine changes the PRG-ROM bank in the same manner:
setPRGBank: sta $8765 lsr a sta $FACE lsr a sta $BA11 lsr a sta $AD2E lsr a sta $EAD5 rts
To reset the mapper, which clears the shift register and sets the PRG-ROM bank mode to 3 (fixing the last bank at $C000 and allowing the 16 KB bank at $8000 to be switched), one need only do a single write to any ROM address with a 1 in bit 7:
resetMapper: lda #$80 sta $8000 rts
Commonly, reset is done with an increment on a negative value to save 2 bytes. Because increment performs two writes, first writing the old value before the incremented one, it is recommended (such as for wider emulator compatibility) that the increment target a value that is negative on both writes, such as the INC opcode ($EE) itself:
resetMapper: inc resetMapper rts
Note that some games do a reset write to each of the 4 registers, even though it is only necessary to do 1 reset write to any register. It is suspected these games do this because of discrete logic implementations of MMC1 on development boards such as the MMC MULTI CHECKER-02, which uses separate shift registers for each MMC1 register.[1]
When the serial port is written to on consecutive cycles, it ignores every write after the first. In practice, this only happens when the CPU executes read-modify-write instructions, which first write the original value before writing the modified one on the next cycle.[2] This restriction only applies to the data being written on bit 0; the bit 7 reset is never ignored. Bill & Ted's Excellent Adventure does a reset by using INC on a ROM location containing $FF and requires that the $00 write on the next cycle is ignored. Shinsenden, however, uses illegal instruction $7F (RRA abs,X) to set bit 7 on the second write and will crash after selecting the みる (look) option if this reset is ignored.[3] This write-ignore behavior appears to be intentional and is believed to ignore all consecutive write cycles after the first even if that first write does not target the serial port.[4]
The following description generally applies to all boards mounting an MMC1 ASIC; refer to the connection variants section on how some registers bits have different meanings on particular circuit boards.
7 bit 0
---- ----
Rxxx xxxD
| |
| +- Data bit to be shifted into shift register, LSB first
+--------- A write with bit set will reset shift register
and write Control with (Control OR $0C),
locking PRG-ROM at $C000-$FFFF to the last bank.
On consecutive-cycle writes, writes to the shift register (D0) after the first are ignored. See Consecutive-cycle writes for more details.
4bit0 ----- CPPMM ||||| |||++- Nametable arrangement: (0: one-screen, lower bank; 1: one-screen, upper bank; ||| 2: horizontal arrangement ("vertical mirroring", PPU A10); ||| 3: vertical arrangement ("horizontal mirroring", PPU A11) ) |++--- PRG-ROM bank mode (0, 1: switch 32 KB at $8000, ignoring low bit of bank number; | 2: fix first bank at $8000 and switch 16 KB bank at $C000; | 3: fix last bank at $C000 and switch 16 KB bank at $8000) +----- CHR-ROM bank mode (0: switch 8 KB at a time; 1: switch two separate 4 KB banks)
Although some tests have found that all versions of the MMC1 seems to reliably power on in the last bank (by setting the "PRG-ROM bank mode" to 3); other tests have found that this is fragile. Several commercial games have reset vectors every 32 KiB, but not every 16, so evidently PRG-ROM bank mode 2 doesn't seem to occur randomly on power-up.
4bit0 ----- CCCCC ||||| +++++- Select 4 KB or 8 KB CHR bank at PPU $0000 (low bit ignored in 8 KB mode)
MMC1 can do CHR banking in 4KB chunks. Known carts with CHR-RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.
4bit0 ----- CCCCC ||||| +++++- Select 4 KB CHR bank at PPU $1000 (ignored in 8 KB mode)
4bit0
-----
RPPPP
|||||
|++++- Select 16 KB PRG-ROM bank (low bit ignored in 32 KB mode)
+----- MMC1B and later: PRG-RAM chip enable (0: enabled; 1: disabled; ignored on MMC1A)
MMC1A: Bit 3 bypasses fixed bank logic in 16K mode (0: fixed bank affects A17-A14;
1: fixed bank affects A16-A14 and bit 3 directly controls A17)
The high bit does not select a PRG-ROM bank. MMC1 with 512 KiB was supported by re-using a line from the CHR banking controls. (See below.)
MMC1A's 'R' bit logic was originally designed to support a hypothetical circuit board that connects the MMC1's A17 output to PRG-RAM A13, meaning a circuit board with 128 KiB of PRG-ROM and 16 KiB of PRG-RAM. Such a circuit board was never produced; games needing 16 KiB of PRG-RAM ended up using the SOROM or SZROM circuit boards that support more than 128 KiB of PRG-ROM and bank-switch PRG-RAM using other means.
Boards designed for 32 KiB PRG-ROM (SEROM, SHROM, and SH1ROM), such as Dr. Mario, do not connect PRG A14 to the MMC1; instead A14 is connected directly to the NES. As a result, register $E000 is completely without function, and the entire 32 KiB of PRG-ROM appear unbanked from CPU $8000-$FFFF. For compatibility with these, an emulator may switch to PRG bank 0 at power-on.
SNROM, which only supports 8 KiB of CHR-ROM/-RAM, uses the upper CHR bank select line coming out of the mapper (CHR A16; bit 4 of bank number) as an additional chip enable for the PRG-RAM.[1]
4bit0 ----- ExxxC | | | +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode) +----- PRG-RAM disable (0: enable, 1: open bus)
4bit0 ----- ExxxC | | | +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode) +----- PRG-RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)
All three address only 8 KiB of CHR-ROM/-RAM and use the upper CHR lines to increase the PRG-RAM size from 8 to 16 KiB (SOROM) or 32 KiB (SXROM), and to increase the PRG-ROM size from 256 to 512 KiB (SUROM and SXROM).
4bit0 ----- PSSxC ||| | ||| +- Select 4 KB CHR-RAM bank at PPU $0000 (ignored in 8 KB mode) |++--- Select 8 KB PRG-RAM bank +----- Select 256 KB PRG-ROM bank
4bit0 ----- PSSxC ||| | ||| +- Select 4 KB CHR-RAM bank at PPU $1000 (ignored in 8 KB mode) |++--- Select 8 KB PRG-RAM bank (ignored in 8 KB mode) +----- Select 256 KB PRG-ROM bank (ignored in 8 KB mode)
The SOROM board only implements the upper S bit, while the SUROM board only implements the P bit. For SXROM, the upper S (bit 3) selects the SRAM's A14, and the lower S (bit 2) selects A13[5].
The 256 KB PRG bank selection applies to all the PRG area, including the normally "fixed" bank. It is therefore sometimes described as an "outer bank".
In 4KB CHR bank mode, SNROM's E bit and SO/U/XROM's P and S bits in both CHR bank registers must be set to the same values, or the PRG-ROM and/or RAM will be bankswitched/enabled as the PPU renders. As there is not much of a reason to use 4 KB bankswitching with CHR-RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.
SZROM addresses only 64 KiB of CHR-ROM/-RAM and uses the remaining CHR line to increase the PRG-RAM size from 8 to 16 KiB.
4bit0 ----- RCCCC ||||| |++++- Select 4 KB CHR-ROM bank at PPU $0000 (low bit ignored in 8 KB mode) +----- Select 8 KB PRG-RAM bank
4bit0 ----- RCCCC ||||| |++++- Select 4 KB CHR-ROM bank at PPU $1000 (ignored in 8 KB mode) +----- Select 8 KB PRG-RAM bank (ignored in 8 KB mode)
SZROM behaves similarly to SOROM, except that the PRG-RAM bank is a controlled by a different bit, and enough CHR is present that 4K bankswitching is desirable. The only currently-known game on SZROM is A Ressha de Ikou.
SZROM can be detected by a NES2.0 header specifying 8 KiB of PRG-RAM, 8 KiB of PRG-NVRAM, and 16 KiB or more of CHR.
The connection variants of SxROM that apply to registers $A000 and $C000 can be amalgamated as follows:
4bit0 ----- EDCBA ||||| ||||+- CHR A12 |||+-- CHR A13 if CHR >= 16 KiB ||+--- CHR A14 if CHR >= 32 KiB; and PRG-RAM A13 if PRG-RAM size is 32 KiB |+---- CHR A15 if CHR >= 64 KiB; and PRG-RAM A13 if PRG-RAM size is 16 KiB | or PRG-RAM A14 if PRG-RAM size is 32 KiB +----- CHR A16 if CHR = 128 KiB; and PRG-ROM A18 if PRG-ROM size is 512 KiB
The E bit also acts as a PRG-RAM disable for SNROM (PRG-ROM size <= 256 KiB, CHR-RAM size = 8 KiB, PRG-RAM size = 8 KiB), though this is merely for write protection and not strictly required for compatible emulation.
The D bit used by SOROM (16k PRG-RAM) and SXROM (32 KiB PRG-RAM) controls a different address line depending on the board type. Using A13 for D with both boards and A14 for C will work, but will break SXROM battery save file compatibility with standard implementations.
This board, used with the Famicom Network System (FCNS), features 64 big-endian 16-bit words of EEPROM in addition to up to 32 KB of battery-backed PRG-RAM. Because FCNS cartridges are not on the PPU bus, all PPU-related MMC1 outputs are repurposed for EEPROM and PRG-RAM storage. The EEPROM's data output is mapped to $6000-7FFF bit 0 when enabled, and its command and data interface can be found in the 93LC46 datasheet. Note that open bus for this board is card open bus, which is open bus on the card side of the FCNS, not the console side.
2ME is assigned NES 2.0 MMC1 submapper 6 and uses an MMC1B.
7 bit 0 ---- ---- ...I PPEE | |||| | ||++- EEPROM CS (01 = enabled, otherwise disabled) | ++--- PRG-ROM bank mode (see standard register definition) +------ EEPROM DI enable (0 = DI forced to 0, 1 = DI output enabled)
The graphics-related bits here are repurposed for EEPROM enables. Because the MMC1's PPU A12-10 inputs are grounded on the 2ME board, settings that would normally vary based on PPU fetches such as the nametable arrangement and active CHR register are instead fixed.
7 bit 0 ---- ---- ...O RRCI | |||| | |||+- EEPROM DI | ||+-- EEPROM CLK | |+--- PRG-RAM A13 | +---- PRG-RAM A14 +------ PRG-RAM /CE, and EEPROM DO +OE (0 = PRG-RAM enabled, 1 = EEPROM DO enabled)
7 bit 0 ---- ---- ...D PPPP | |||| | ++++- PRG-ROM bank (see standard register definition) +------ $6000-7FFF disable (0 = enabled, 1 = disabled)
If $6000-7FFF is disabled, then neither PRG-RAM nor EEPROM can be accessed through this region and reads return card open bus. EEPROM can still be written, however, because the DI input does not use this region.
The following SxROM boards are known to exist:
| Board | PRG-ROM | PRG-RAM | CHR | Comments |
|---|---|---|---|---|
| SAROM | 64 KB | 8 KB | 16 / 32 / 64 KB ROM | NES only |
| SBROM | 64 KB | 16 / 32 / 64 KB ROM | NES only | |
| SCROM | 64 KB | 128 KB ROM | NES only | |
| SC1ROM | 64 KB | 128 KB ROM | Uses 7432 for 28-pin CHR-ROM | |
| SEROM | 32 KB | 16 / 32 / 64 KB ROM | ||
| SFROM | 128 / 256 KB | 16 / 32 / 64 KB ROM | ||
| SF1ROM | 256 KB | 64 KB ROM | PRG uses standard 32-pin EPROM pinout | |
| SFEXPROM | 256 KB | 64 KB ROM | Patches PRG at runtime to correct a bad mask ROM run. | |
| SGROM | 128 / 256 KB | 8 KB RAM/ROM | ||
| SHROM | 32 KB | 128 KB ROM | NES only | |
| SH1ROM | 32 KB | 128 KB ROM | Uses 7432 for 28-pin CHR-ROM | |
| SIROM | 32 KB | 8 KB | 16 / 32 / 64 KB ROM | Japan Only |
| SJROM | 128 / 256 KB | 8 KB | 16 / 32 / 64 KB ROM | |
| SKROM | 128 / 256 KB | 8 KB | 128 KB ROM | |
| SLROM | 128 / 256 KB | 128 KB ROM | ||
| SL1ROM | 64 / 128 / 256 KB | 128 KB ROM | Uses 7432 for 28-pin CHR-ROM | |
| SL2ROM | 128 / 256 KB | 128 KB ROM | CHR uses standard 32-pin EPROM pinout | |
| SL3ROM | 256 KB | 128 KB ROM | Uses 7432 for 28-pin CHR-ROM | |
| SLRROM | 128 / 256 KB | 128 KB ROM | Difference from SLROM unknown | |
| SMROM | 256 KB | 8 KB RAM | Japan Only | |
| SNROM | 128 / 256 KB | 8 KB | 8 KB RAM/ROM | |
| SOROM | 128 / 256 KB | 16 KB | 8 KB RAM/ROM | |
| STROM | Not MMC1, actually NROM | |||
| SUROM | 512 KB | 8 KB | 8 KB RAM/ROM | |
| SXROM | 128 / 256 / 512 KB | 32 KB | 8 KB RAM/ROM | Japan Only |
| SZROM | 128 / 256 KB | 16 KB | 16-64 KB ROM | Japan Only |
Even if the SOROM and SZROM boards utilizes a battery, it is connected to only one PRG-RAM chip. The first RAM chip will not retain its data, but the second one will.
At least six different versions of the MMC1 are known to exist: MMC1, MMC1A, MMC1B1, MMC1B2, MMC1B2F, MMC1B3. The known differences relate to bit 4 of $E000.
The MMC1 most commonly exists in a 24-pin shrink-DIP package. An SOIC-24 incarnation MMC1B2F has been observed inside of a JRA-PAT Famicom Network System card.
Boards using an MMC1 may contain a battery connected to the PRG-RAM's power line to preserve the data. Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors. A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery as part of UL compliance. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capacity, and saves are lost much more easily on those boards.
Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88). Two games (1, 2) are known to rely on MMC1A behavior, writing values between $10 and $1F to the PRG bank register, write to WRAM at $6000-$7FFF, and expect the write to succeed.
AX5904 is a third-party clone of the MMC1A.
Categories: Nintendo licensed mappers, In NesCartDB, Mappers with large PRG RAM, ASIC mappers, NES 2.0 mappers with submappers, Mappers with single-screen mirroring