| Company | Nintendo |
| Games | 3 in NesCartDB |
| Complexity | ASIC |
| Boards | FJROM, FKROM |
| Pinout | MMC4 pinout |
| PRG ROM capacity | 256K |
| PRG ROM window | 16K + 16K fixed |
| PRG RAM capacity | 8K |
| PRG RAM window | 8K |
| CHR capacity | 128K |
| CHR window | 4K + 4K (triggered) |
| Nametable mirroring | H or V, switchable |
| Bus conflicts | No |
| IRQ | No |
| Audio | No |
| iNES mappers | 010 |
The Nintendo MMC4 is an ASIC mapper, used on the FxROM board set. The iNES format assigns mapper 10 to these boards. The chip first appeared in August 1988.
Nintendo's MMC2, used in PxROM boards, is a similar mapper with 8 KB switchable PRG ROM banks, a 24 KB fixed PRG ROM bank, no PRG RAM, and a slightly different behaviour in auto-switching on the left (low) pattern table. This page only explains the differences, see MMC2 for full details on the rest of the mapper.
When the PPU reads from specific tiles in the pattern table during rendering, the MMC4 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolising the CPU.
The MMC4 has 6 registers at $A000-$AFFF, $B000-$BFFF, $C000-$CFFF, $D000-$DFFF, $E000-$EFFF and $F000-$FFFF. Only $A000-$AFFF is covered here. For the rest of the registers, see MMC2.
7 bit 0
---- ----
xxxx PPPP
||||
++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
The MMC4 is implemented in a 44-pin TQFP package: MMC4 pinout
Only one revision is known to exist.
Categories: Nintendo licensed mappers, Mappers triggering on reads, ASIC mappers, In NesCartDB