NES 2.0 Mapper 534 denotes an MMC3-based multicart mapper with an optional (C)NROM-like PRG and CHR banking modes.
These registers function identically to a normal MMC3, except that the scanline counter latch register ($C000) takes the inverted value (XOR $FF) compared to a regular MMC3.
Mask: $E003 D~7654 3210 --------- XYBB CPPp |||| |||+- PRG A17 if Y=1 ||++-|+++- PRG A21..A18 ||++-+---- CHR A19..A17 |+-------- PRG A17 mode | 0: PRG A17=MMC3 PRG A17 (256 KiB inner PRG bank size) | 1: PRG A17=p (128 KiB inner PRG bank) +--------- CHR A17 mode 0: CHR A17=MMC3 CHR A17 (256 KiB inner CHR bank size) 1: CHR A17=C (128 KiB inner CHR bank)
Mask: $E003 D~7654 3210 --------- .... ..?M +- 0: CPU $8000-$FFFF reads PRG-ROM 1: CPU $8000-$FFFF reads solder pad (D0/D1)
Mask: $E003 D~7654 3210 --------- ...M CCCC | ++++- CHR A16..A13 in CNROM mode, | ignored otherwise +------ 1=CNROM-128 mode, 0=CNROM-256 mode
The CNROM bit matters when the Lock bit is set: In CNROM-256 mode, bits 0 and 1 are still writable, in CNROM-128 mode, only bit 0 is writable.
Mask: $E003 D~7654 3210 --------- L..C .?PP | | ++- PRG Banking Mode | | 0: MMC3 | | 1: NROM-128: PRG A14=MMC3 PRG A14 | | 2: NROM-128: Same as 1 | | 3: NROM-256: PRG A14=CPU A14 | +------ CHR Banking Mode | 0: MMC3 | 1: CNROM +--------- Lock registers $6000-$6003 except $6002.0/1
NROM PRG banking mode is implemented by holding the MMC3 clones' CPU A13 and A14 input low. This means that...
CNROM CHR banking mode is implemented by using register $6002 as a source for an 8 KiB inner bank number instead of the MMC3's CHR registers.
Categories: MMC3-like mappers, Mappers with CHR RAM, Mappers with scanline IRQs, Multicart mappers